2.1.Introduction:

Any hardware module in VHDL is described in "entity concept".Entity needs minimum Entity declaration and an Architecture to describe any design.Other design units are Package declaration,package body and configuration, which will be discussed later.VHDL is not case sensitive language,all the reserved words of VHDL language represented in caps either in example or in the syntax.

2.2.Entity Declaration:-

In the Entity Declaration input, output and inout ports are declared through which a module will communicate to the other modules or to the system.

Syntax:-

ENTITY entity_name IS generics(optional) PORT( port name : mode type; port name : mode type ); END entity_name;

entity_name indicates the name of the entity. Port name is the identifier through which data will be passed. generics specifies the parametrized component. mode indicates direction of data flow like in(put) or out(put) or in(put)out(put) or buffer...