4.2:Data Types:-

Data type is an attribute which specify which type of data an object can hold. Data types which are frequently used in VHDL will be discussed here.

4.2.1 STD_LOGIC:-

STD_LOGIC holds any one of the following values

'0', -- force 0

'1', -- force 1

'w', -- weak unknown

'u', -- uninitialized

'z', -- impedance

'h', -- weak 1

'l', -- weak 0

'x' and -- force unknown

'-' -- don't care.

Example 4.1:- SIGNAL a : STD_LOGIC; a <= '0';

Example 4.2:- VARIABLE a : STD_LOGIC; a := '1';

4.2.2 STD_LOGIC_VECTOR:-

STD_LOGIC_VECTOR holds an one dimensional array values as same as std_logic

Example 4.3:- SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; -- Here ":=" is used to initialize the signal value this is recommended only in test bench not for writing RTL code...

4.1.Introduction:-

Data objects hold the value in a specified format, which will be helpful to interpret the type of information. The specific characteristics of the data objects explains using the "data types". "Operators" are functions, used to produce other functions.

4.2. Data Objects:-

Data Objects are classified in to four types. They are listed below

i. Constants

ii. Signals

iii. Variables

iv. Files

4.2.1. Constants:-

Constant hold the value, which cannot be changed during the run time. Constants generally used for easier readability. It can be used in Package, Entity or in the Architecture. If it is used inside the package then that constant will be used as global wherever the package is used across several entities. If the constant used under the entity then the constant may be used in different architectures. When the constant is used inside architecture then it will be local to that architecture.

Example 4.1:-...